It is well known to employ multiple microprocessors or microcomputers in a system such that each microcomputer or microprocessor is dedicated to carrying out some particular function. In a coordinated system, however, it is necessary that these units communicate with each other and share operative results and perhaps a common data base. The typical method for sharing information and data between processing units is to provide a common memory to which each microprocessor or microcomputer has access on a shared basis. This is a fairly simple, straightforward scheme in which one unit is allowed random access to the memory alternatively with the other.
An obvious disadvantage of the shared memory technique is that only one processor unit has access to the memory at any given time. This may result in one unit idly standing by while awaiting access to the memory.
This problem has been particularly acute in the field of programmable controllers wherein it is often desirable or necessary to interface the programmable controller to another computer for programming or monitoring purposes. Although the shared memory technique lends itself to this interfacing need, it suffers from the same obvious problem that only one unit at a time has access to the shared memory. With the programmable controller dedicated to the control of some critical process, all undue delay must be avoided.
Accordingly, it is an object of the present invention to provide a method and apparatus whereby data processing units can exchange information with each other through a common memory without delay incurred by limiting access to the memory to only one data processing unit at a time.